The SCALE-2 chipset helps designers to optimize switching performance, reliability and scalability as well as application flexibility and time-to-market. It is specifically optimized to fit various IGBTs and applications ranging from 150A to 3600A and 600V to 6500V but is also preconfigured to allow application-specific customization.

With the SCALE-2 chipset, CONCEPT introduces its next-generation technology platform for scalable IGBT and power MOSFET gate drivers introducing major advances in dynamic performance, accuracy, functionality, flexibility and time-to-market. The design fully employs the methodology of the CONCEPT SCALE drivers that are used in large item numbers and have been tried and tested within a great diversity of applications. The SCALE-2 chipset includes several variants of secondary-side Intelligent Gate Driver (IGD) ASICs and a primary-side dual channel Logic-to-Driver Interface (LDI) ASIC. 

The combination of state-of-the-art analog capabilities with moderate digital feature size yields an optimum cost-performance ratio.

The highly integrated SCALE-2 gate driver chipset implements all required functionality and allows easy power scaling up to 60A / 20W and beyond. The pre-driver stages are primarily designed to assure optimum performance for direct driving of external n-type DMOS by using separate gate resistors for independent control of turn-on and turn-off.

Intelligent Gate Driver (IGD) ASIC

A micrograph of a prototype gate driver ASIC is shown in Fig. 1. Various bonding variants are used to control the specific functionality of different standard products including options for bidirectional-signal-transformer and fiber-optic interfaces.  The ASIC also contains a semi-custom array for additional degrees of customization. Advanced control options may be realized through a single programming metal mask. The semi-custom array contains preconfigured cells such as analog comparators, logic gates, primitive devices and pads.

The IGD ASIC provides a regulated +15V gate-emitter voltage for the turn-on and on-state by adjusting the emitter potential at the “Vee” pin (see Fig. 3) with options to set a custom-specific gate-emitter voltage.

The ASIC incorporates circuitry to realize closed-loop control of both the rate of rise [1] and clamping level [2] of the collector-emitter voltage of the IGBT at turn-off. Faster response of the Active Clamping process, reduced turn-off switching losses and enhanced short-circuit turn-off capability can then be achieved.

Logic-to-Driver Interface (LDI) ASIC

A micrograph of a Logic-to-Driver Interface ASIC is shown in Fig. 2. The ASIC implements a dual-channel bidirectional transformer interface, a scalable DC/DC converter with dedicated startup sequence as well as scalable setup and fault management.

Bidirectional Transformer Interface

The bidirectional transformer interface transmits both command and fault signals via short single pulses to achieve minimum command delay. In case of a collision, the fault signal dominates both the command signal and dv/dt induced noise currents by means of a longer pulse duration. The asynchronous fault transfer method also allows the special timing requirements of parallel-connected IGBTs or multi-level converter topologies to be managed, since any fault condition will be available at the primary side within one microsecond. A preferred fault-management mode thus reports the fault event in advance of a turn-off of the relevant IGBTs. The delay to shutdown is adjustable at the IGD ASIC. For transformer coupled drivers (see Fig. 3) less than 80ns delay time and ±1ns jitter are achieved.

Operation Modes

Direct Mode allows independent driving of both driver channels. This mode offers the highest flexibility to the customer and is therefore preferred for advanced microcontroller-assisted systems. In half-bridge mode, the ASIC uses only one input as a common command signal and generates two (non-inverted and inverted) outputs. The mode and dead time are adjustable to the needs of the particular application by a single resistor component. A third mode is preconfigured to implement interlock or mutual exclusion upon customer request.

Fault Management

On the primary side, any fault state may be stretched by a Blocking Time. During this time, the relevant channel is kept in the off-state. This time is adjustable and can also be set to zero by a single resistor.

System Integration

CONCEPT's proprietary SCALE-2 chipset serves as a core platform for implementing the next generation of IGBT driver series.

Fig. 4 shows a slightly simplified schematic of a Plug-and-Play IGBT driver for high-voltage IGBT modules up to 6500V with an advanced Active Clamping function. The driver achieves a gate capability of 40A, 6W by using external n-type DMOS for both the gate drive and DC/DC converter output stages. The overall component count is reduced by more than 60% compared to the previous SCALE driver chipset [3].

• Low jitter and drift IGBT drivers
• Switching frequencies up to 750kHz
• Parallel and series-connected IGBTs

• Highly integrated solution
• Fast setup and superior adaptability
• Flexible fault management
• 2-level, 3-level and multilevel topologies
• Reliable, long service life

• Regulated gate-emitter voltage
• Integrated 8A / 0.8W driver core
• Easy scaling up to 60A / 20W
• Separate gate current paths
• Advanced active clamping
• IGBT short-circuit protection
• Secondary-side fault input / output
• Supply under-voltage lockout
• Fiber-optic interfaces *
• Signal transformer interfaces *

• DC/DC power supply circuitry
• Supply under-voltage lockout
• Signal transformer interfaces *
• Failure Status Outputs

• Suitable for IGBTs up to 3300V
• Signal transformer interfaces
• Schmitt-trigger inputs
• Interface for 3.3V...15V logic level
• Compatible to all logic families
• Direct and half-bridge modes
• Very short delay time of <80ns
• Extremely small jitter of <±1ns
• Superior EMC (dv/dt > 100V/ns)

• Suitable for IGBTs up to 6500V
• Signal fiber-optic link
• Signal edge acknowledgement
• Fiber-optic status feedback

* = depends on bonding variant